1. Field of the Invention
The present invention relates to a display memory for storing data to be displayed by a monitor, and, in particular, to a display memory such as a multiport DRAM comprising a frame buffer.
2. Description of the Prior Art
A conventional multiport DRAM, as shown in FIG. 1, for example, is provided with two ports, a serial port PS and a random port PR, and is constructed so that access to a desired address is obtained by an address signal SA.
In a multiport DRAM 101 of this type it is necessary to input an address value from an external source as the address signal SA for specifying a row to be transmitted from a DRAM cell array 3 to a SAM 9 during data transfer.
In addition, in a display system using the multiport DRAM 101 as shown in FIG. 2, when the address value is input to the multiport DRAM 101, an address ADT for data transfer transmitted from a display control unit 73 and an image address ADR for random access transmitted from an image control unit 71 must be selected by a multiplexer 111 because the random access address input signal terminal PR is used.
Accordingly, a multiplexer is required for the data transfer address and the random access address and a circuit is required for control and the like of the multiplexer. A large system is therefore required.
In addition, a delay, specifically, a gate delay is produced in the signal transmission in the multiplexer or multiplexer control system.
This is an obstacle to high speed memory access of the image control unit 71. Specifically, it is difficult to process the image. As outlined above, in order to use one address input signal terminal for both random access and data transfer with a conventional multiport DRAM when the DRAM is incorporated in a display system, a circuit and a multiplexer are necessary to multiplex and control a display system address ADT and an image control address ADT. For this reason the scale of the system is large and, in addition, it is difficult to convert to high speed image processing.